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New Synthetic Test Circuit for the Operational Test of HVDC Thyristor Valve

机译:高压直流可控硅阀门运行试验新型综合测试电路

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摘要

In general, the power handling capability of thyristors in the classical HVDC systems has seen significant progress in the past thirty years. It was known that five or more thyristor levels in a valve section should be tested for the adequate representation in case of valve section composed of twelve or more levels in series. This means that if we adopt the direct testing for the valve section or valve, we need very large testing power, which is not the practical solution. As a result, all HVDC valve manufactures are using synthetic testing method recommended by CIGRE as an alternative to the direct testing.Synthetic testing methods are based on the fact that the HVDC thyristor valve is stressed by current and voltage at different time intervals. The current stress occurs during the conduction interval followed by the voltage stress during the blocking interval of the valve. If we use two separate power sources, one voltage source and one current source, at different time intervals, it is possible to apply the voltage stress and the current stress to the test valve independently. This means that we can minimize the power required for valve test. Voltage and current stresses on a test thyristor valve can be analysed separately in four operation states: off-state and reverse voltage, turn-on, on-state and turn-off state. Key points of synthetic test circuit are how to control the transition intervals from one operation state to another operation state, critically from on-state to off-state or the opposite direction. This paper proposes a new STC (Synthetic Test Circuit) by adopting two-phase chopper with an auxiliary switching circuit for the turn-off of the “so-called isolation thyristor”. Also the proposed STC can minimize the power ratings of the current source equipment by supplying “the gate power of the test thyristors” through the resonant circuit side, not from the current source side. And the gate power of the thyristors in the resonant circuit is supplied through the independent high frequency power source. The proposed STC was tested under the requirement of IEC 9.3.1~9.3.3.
机译:通常,在过去的30年中,经典HVDC系统中晶闸管的功率处理能力取得了显着进步。已知的是,如果阀部分由十二个或更多级串联组成,则应测试阀部分中的五个或更多晶闸管级是否足够。这意味着,如果我们直接对阀段或阀进行测试,则需要非常大的测试能力,这不是实际的解决方案。因此,所有HVDC阀制造商都使用CIGRE推荐的综合测试方法作为直接测试的替代方法。综合测试方法基于以下事实:HVDC晶闸管阀在不同的时间间隔受到电流和电压的应力。电流应力在导通间隔期间发生,随后在阀的阻塞间隔期间发生电压应力。如果我们在不同的时间间隔使用两个单独的电源,一个电压源和一个电流源,则可以将电压应力和电流应力分别施加到测试阀上。这意味着我们可以最大程度地减少阀门测试所需的功率。可以在四个操作状态下分别分析测试晶闸管阀上的电压和电流应力:断开状态和反向电压,接通,接通状态和断开状态。合成测试电路的关键是如何控制从一种工作状态到另一种工作状态的过渡间隔,从临界状态到导通状态到断电状态或相反的方向。本文提出了一种新的STC(综合测试电路),它采用带有辅助开关电路的两相斩波器来关断“所谓的隔离晶闸管”。另外,通过通过谐振电路侧而不是从电流源侧提供“测试晶闸管的栅极功率”,所提出的STC可以使电流源设备的额定功率最小化。谐振电路中晶闸管的栅极功率通过独立的高频电源提供。提议的STC已按照IEC 9.3.1〜9.3.3的要求进行了测试。

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