SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA

摘要

In this work, we are making energy efficient 32-bit ALU by using different classes of LVCMOS IO standard. Here, we are operating our design with operating speed of 4th generation i7 processor in order to test the compatibility of our design with the latest state of the art technology based processor. When there is no demand of peak performance, then we can save 75.2% Clock power, 75% Logic power, 75.36% Signal power, 81.82% I/O power by operating our device with 1GHz frequency in place of maximum 4GHz. LVCMOS25 having 69.65%, 53.48%, 38.77% more power consumption with respect to LVCMOS12, LVCMOS15, LVCMOS 18 at 2.9GHz respectively. In this we used, VERILOG hardware description language, XILINX ISE simulator, and Virtex-6 FPGA and XPower analyzer.