In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.
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机译:在这项工作中,我们为垂直纳米线金属氧化物半导体场效应晶体管提供了一种新型的自对准后栅制造工艺。该制造方法允许曝光剂量定义的栅极长度和本征沟道段的局部直径减小,同时保持较厚的高掺杂访问区。使用该工艺,制造出具有良好导通和截止性能的InAs纳米线晶体管,其Q = gm,max / SS = 8.2,高于以前报道的任何垂直纳米线MOSFET。
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