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Design and characterization of layered tunnel barriers for nonvolatile memory applications

机译:用于非易失性存储器应用的分层隧道势垒的设计和表征

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摘要

The main limitations of floating gate memory devices (Flash memory) are the long program (microsecond) and erase times (millisecond) inherent to the charging of floating gates using Fowler-Nordheim tunneling. An alternative to the integration of homogeneous dielectric tunnel barriers present in standard Flash memory is to use ?layered? tunnel barriers made of high-k heterostructures. This allows for an effective lowering in barrier height under applied bias, resulting in shorter write/erase times while maintaining long retention times.ududTo assess these types of dielectric structures, tunneling probability simulations were performed using an effective mass-model, allowing us to predict current-voltage (I-V) characteristics and optimize the layered tunnel barrier structure. Based on our results, we correlated dielectric constants and band offsets with respect to silicon in order to help identify possible materials from which to construct these layered barriers. This survey allowed for the determination of promising high-k materials heterostructures: Si3N4 / Al2O3 / Si3N4 / Si3N4 and HfO2 / Al2O3 / HfO2.ududWe performed a series of physical and electrical characterization experiments on single-layer as well as two- and three-layer structures of Si3N4, Al2O3, and HfO2. Transmission electron microscopy and I-V measurements were used to correlate the physical effects of high-temperature annealing on the electrical properties of the films, allowing us to determine the ideal processing conditions. Construction of Fowler-Nordheim plots from experimental I-V data gave qualitative evidence of barrier lowering in the multi-layer structures.ududWe developed a bias-dependent photoemission technique for quantitative determination of the band-offsets between silicon and our dielectric barriers, which is found to be highly dependent on the applied bias. For SiO2 (and other single-layer materials), image potential barrier lowering simulations predict the barrier profile as a function of voltage, allowing us to report the band-offsets for these materials in a more complete way than was previously possible. Also, by characterizing multi-layer structures of HfO2 and Al2O3, we have been able to quantitatively measure the effective barrier height of these structures over a wide range of biases and prove barrier lowering. Analysis by an electrostatic model allowed us to accurately simulate the barrier lowering results over all voltage ranges.
机译:浮栅存储设备(闪存)的主要局限性是使用Fowler-Nordheim隧道对浮栅充电所固有的长程序(微秒)和擦除时间(毫秒)。替代标准闪存中存在的均匀介质隧道势垒的一种替代方法是使用“分层”。高k异质结构制成的隧道势垒。这样可以在施加偏压的情况下有效降低势垒高度,从而缩短写入/擦除时间,同时保持较长的保留时间。 ud ud为了评估这些类型的介电结构,使用有效的质量模型进行了隧道概率模拟,我们预测电流-电压(IV)特性并优化分层隧道势垒结构。根据我们的结果,我们将相对于硅的介电常数和能带偏移进行了关联,以帮助确定可能用来构造这些分层势垒的材料。这项调查可以确定有前途的高k材料异质结构:Si3N4 / Al2O3 / Si3N4 / Si3N4和HfO2 / Al2O3 / HfO2。 ud ud我们对单层以及两层进行了一系列物理和电学表征实验Si3N4,Al2O3和HfO2的三层结构。使用透射电子显微镜和I-V测量来关联高温退火对薄膜电性能的物理影响,从而使我们能够确定理想的加工条件。从实验IV数据构建Fowler-Nordheim图可以得到多层结构中势垒降低的定性证据。 ud ud我们开发了一种偏置相关的光发射技术,用于定量确定硅与介电势垒之间的能带偏移。被发现高度依赖于所施加的偏置。对于SiO2(和其他单层材料),图像势垒降低模拟可以预测势垒曲线随电压的变化,从而使我们能够以比以前更完整的方式报告这些材料的带隙。另外,通过表征HfO2和Al2O3的多层结构,我们已经能够在很大范围的偏压下定量测量这些结构的有效势垒高度,并证明势垒降低。通过静电模型进行的分析使我们能够在所有电压范围内准确模拟势垒降低的结果。

著录项

  • 作者

    Casperson Julie Diane;

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  • 年度 2004
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  • 原文格式 PDF
  • 正文语种 {"code":"en","name":"English","id":9}
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