Iterative RLC models for interconnect delay optimization in VLSI routing algorithms

摘要

Buffer insertion (van Ginneken, 1990), and wire-sizing techniques (Lillis, Cheng and Lin, 1996) have been widely used to minimize global interconnect delay path between interconnect source and sink points. These techniques rely on delay models (Pileggi, 1995) to estimate buffer insertion points – from simple first order linear model (Elmore, 1948) to more complex moment matching techniques (Ismail, Friedman and Neves, 1999a). Thus, interconnect analysis and modeling is of paramount importance in realizing a successful global interconnect routing. For effective buffer insertion point estimation, both source-to-sink and sink-tosource delay estimation may be used (Shaikh-Husin and Khalil- Hani, 2007). As VLSI fabrication technology scales to smaller feature sizes and larger layout areas, global interconnect delay increasingly dominates device delay (Bakoglu, 1990).