This project report reports the development of The design and simulation of 8×1 passively quenched Single Photon Avalanche Diode (SPAD) array. This research is covered on the development and characterization of a passive quenching circuit by using Silterra 180nm CMOS technology. The main motivation of this research is to design a passive quenching circuit using thin gate devices with low voltage technology design on-chip with 4-bit counter to improve the counting rate. Hence, the passive quenching circuit design on-chip would enable the capability to perform at higher speed which is more than 100MHz. The simulation and design of the passive quenching circuit will be accomplished using CADENCE tools. To perform the simulation of a passive quenching circuit in Cadence, Single Photon Avalanche Diode (SPAD) simulation model circuit is adopted and designed in CADENCE Virtuoso Schematic to generate the photon detector signal to the passive quenching circuit. The simulation characterization is implemented on single SPAD pixel and 8×1 SPAD array. The dead time for a single pixel is 9.524ns. Therefore, the circuit would promise at high frequency rate at 106MHz
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