In the SoC development, the compatibility of IP cores is one of the challenges that need to be addressed carefully. Most of the time, IP cores is having different input output specifications with new platform. The Wishbone SoC interconnection Architecture is aim to provide a good solution for SoC integration issues by having common interface specifications. In this project, the Wishbone on-chip computer bus for 32-bit cores is implemented in system verilog along with three different arbitration schemes which are fixed priority, round robin, and priority control. On top of that, the optimum transfer size for Wishbone bus in terms of bus throughput and average wait cycle is presented as well. It is found that the optimum transfer size for Wishbone bus is 64 bytes. Finally, the Wishbone bus is used to examine the bus performance of different arbitration schemes in Modelsim simulation. Round robin arbitration scheme is the best among three arbitration schemes in terms of bus throughput, logic complexity, and maximum wait cycle.
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