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Verification of RTL generated from scheduled behavior in a high-level synthesis flow

机译：验证从高级综合流程中的计划行为生成的RTL

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Pranav Ashar; Subhrajit Bhattacharya; Anand Raghunathan; Akira Mukaiyama;
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年度 1998
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1. Verification of Scheduling of Conditional Behaviors in High-Level Synthesis [J] . Chouksey Ramanuj, Karfa Chandan IEEE transactions on very large scale integration (VLSI) systems . 2020,第7期

机译：高级合成中有条件行为调度的验证
2. A High-level Synthesis Design Flow from ESL to RTL with Multi-parametric Optimization Objective [J] . Anirban Sengupta, Reza Sedaghat IETE Journal of Research . 2011,第2期

机译：具有多参数优化目标的从ESL到RTL的高级综合设计流程
3. An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis [J] . Karfa C., Sarkar D., Mandal C., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2008,第3期

机译：高级综合中计划验证的等效检查方法
4. Verification of RTL generated from scheduled behavior in a high-level synthesis flow [C] . Ashar, P., Bhattacharya, . 1998

机译：验证从高级综合流程中的调度行为生成的RTL
5. Applications of Formal And Semi-formal Verification on Software Testing, High-level Synthesis And Energy Internet [D] . Gao, Min. 2018

机译：正式和半正式验证在软件测试，高级综合和能源互联网中的应用
6. Effects of self-generated rules on the development of schedule-controlled behavior. [O] . I S Rosenfarb, M C Newland, S E Brannon, 1992

机译：自我生成的规则对进度控制行为发展的影响。
7. A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool [O] . Nazanin Mansouri, Range Vemuri 2008

机译：自动验证综合RTL设计并将其与高级综合工具集成的方法
8. Beta: Behavioral Testability Analyzer and Its Application to High-Level TestGeneration and Synthesis for Testability [R] . Chen, C. 1992

机译：Beta：行为可测性分析器及其在高级测试生成和可测性综合中的应用

Verification of RTL generated from scheduled behavior in a high-level synthesis flow

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