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1Signal Integrity Verification of Multi-Chip Links using Passive Channel Macromodels

机译：1使用无源信道宏模型验证多芯片链路的信号完整性

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Ro Chinea; Stefano Grivet-talocia; Senior Member; Haisheng Hu; Piero Triverio; Dierk Kaller; Claudio Siviero; Martin Kindscher;
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年度 2014
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1. Signal Integrity Verification of Multichip Links Using Passive Channel Macromodels [J] . Chinea A., Grivet-Talocia S., Hu H., Components, Packaging and Manufacturing Technology, IEEE Transactions on . 2011,第6期

机译：使用无源通道宏模型的多芯片链接的信号完整性验证
2. Verification of multichannel electrode array integrity by use of cross-channel correlations [J] . Swindale Nicholas V., Spacek Martin A. Journal of Neuroscience Methods . 2016,第Null期

机译：使用跨通道相关性验证多通道电极阵列的完整性
3. Experimental verification on the integrity and performance of the passive residual heat removal system for a SMART design with VISTA-ITL [J] . Byung-Yeon Min, Hyun-Sik Park, Yong-Chul Shin, Annals of nuclear energy . 2014,第sepa期

机译：具有VISTA-ITL的SMART设计的被动余热去除系统的完整性和性能的实验验证
4. Passive delay-based macromodels for Signal Integrity verification of multi-chip links [C] . Chinea A., Triverio P., Grivet-Talocia S. Signal Propagation on Interconnects . 2010

机译：基于被动延迟的宏模型，用于多芯片链路的信号完整性验证
5. Causality verification and enforcement for microelectronic package macromodels. [D] . Aboutaleb, Hazem A. 2014

机译：微电子封装宏模型的因果关系验证和执行。
6. Involvement of the S4-S5 linker and the C-linker domain regions to voltage-gating in plant Shaker channels: Comparison with animal HCN and Kv channels [O] . Manuel Nieves-Cordones, Isabelle Gaillard 2014

机译：S4-S5接头和C接头结构域区域参与植物振荡器通道的电压门控：与动物HCN和Kv通道的比较
7. Signal Integrity Verification of Multichip Links Using Passive Channel Macromodels [O] . Chinea Alessandro, Grivet-Talocia S., Hu Haisheng, 2011

机译：使用无源通道宏模型的多芯片链接的信号完整性验证
8. Low-power multi-chip module and board-level links for data transfer [R] . Carson, R. F. , Hardin, T. L. , Warren, M. E. , 1997

机译：用于数据传输的低功耗多芯片模块和板级链路

1Signal Integrity Verification of Multi-Chip Links using Passive Channel Macromodels

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