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Two-dimensional (2D) transition metal dichalcogenide semiconductor field-effect transistors: the interface trap density extraction and compact model

机译:二维(2D)过渡金属二硫化二氢半导体场效应晶体管:界面陷阱密度提取和紧凑模型

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摘要

A surface potential-based low-field drain current compact model is presented for two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductor field-effect transistors that takes into account the effect of interface trap states on device current-voltage (Ids-Vgs) characteristics and transconductance gm. The presence of interface trap states detrimentally affects device Ids-Vgs performance. Minimal work exists on the extraction of trap states (cm-2 eV-1) of MoS2/high-K dielectric/metal-gate stacks. Additionally, there is a lack of compact models for 2D TMD MOSFETs that can take into account the effect of trap states on device Ids-Vgs performance. This study presents a method to extract the interface trap distribution of MoS2 MOSFETs using a compact model. Presented as part of the model is a surface potential/interface trap charge self-consistent calculation procedure and a drain current expression that does not need numerical integration. The model is tested against reported experimental Ids-Vgs data, and excellent agreement is found between the experiment and the model.
机译:提出了一种基于表面电势的低场漏极电流紧凑模型,该模型针对二维(2D)过渡金属二卤化二硫(TMD)半导体场效应晶体管,该模型考虑了界面陷阱状态对器件电流-电压(Ids- Vgs)特性和跨导gm。接口陷阱状态的存在会不利地影响设备Ids-Vgs的性能。 MoS2 /高K介电/金属栅叠层的陷阱态(cm-2 eV-1)的提取工作很少。此外,缺乏2D TMD MOSFET的紧凑模型,该模型可以考虑陷阱状态对器件Ids-Vgs性能的影响。这项研究提出了一种使用紧凑模型提取MoS2 MOSFET的界面陷阱分布的方法。作为模型的一部分,提供了一个表面电势/界面陷阱电荷自洽计算程序以及一个无需数值积分的漏极电流表达式。针对报告的实验Ids-Vgs数据对模型进行了测试,并且在实验与模型之间发现了极好的一致性。

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