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A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates

机译：用于估算CmOs逻辑门的最小工作电压（VDDmin）的闭合表达式

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Hiroshi Fuketa; Satoshi Iida; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura;
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年度 2011
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1. Minimum Operating Voltage Due to Intrinsic Noise in Subthreshold Digital Logic in Nanoscale CMOS [J] . Francisco Veirano, Fernando Silveira, Lirida Naviner Journal of Low Power Electronics . 2016,第1期

机译：纳米级CMOS中亚阈值数字逻辑中固有噪声引起的最低工作电压
2. Circuit-Level Modeling of SRAM Minimum Operating Voltage Vddmin in the C40 Node [J] . Lorenzo Ciampolini, Siddharth Gupta, Olivier Callen, Journal of Low Power Electronics . 2012,第1期

机译：C40节点中SRAM最低工作电压Vddmin的电路级建模
3. Closed expressions for power dissipations of CMOS logic gates and their application to CMOS circuitries [J] . Hiroaki Shikano, Tomochika Harada, Tadayoshi Enomoto 電子情報通信学会技術研究報告. VLSI設計技術. VLSI Design Technologies . 2001,第695期

机译：CMOS逻辑门功耗的封闭式及其在CMOS电路中的应用
4. A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates [C] . Fuketa Hiroshi, Iida Satoshi, Yasufuku Tadashi, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) . 2011

机译：用于估计CMOS逻辑门的最小工作电压（V DDmin ）的封闭形式
5. Timing analysis of CMOS logic gates in deep submicron VLSI design. [D] . Jiang, Xueping. 2005

机译：深亚微米VLSI设计中CMOS逻辑门的时序分析。
6. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications [O] . Yasunori Takeda, Kazuma Hayasaka, Rei Shiwaku, -1

机译：为低压可穿戴传感器应用而优化的超薄印刷有机TFT CMOS逻辑电路的制造
7. Increasing Minimum Operating Voltage (VDDmin) with Number of CMOS Logic Gates and Experimental Verification with up to 1Mega-Stage Ring Oscillators [O] . Taro Niiyama, Zhe Piao, Koichi Ishida, 2015

机译：通过CmOs逻辑门数和最高1兆级环形振荡器的实验验证来提高最小工作电压（VDDmin）
8. Behavior of faulty double BJT BiCMOS logic gates [R] . Menon, Sankaran M., Malaiya, Yashwant K., Jayasumana, Anura P. 1992

机译：有缺陷的双BJT BiCmOs逻辑门的行为

A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates

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