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Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization

机译：时间驱动单元布局解压缩通过临界面积最小化实现产量优化

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Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada;
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年度 2015
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1. Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization [J] . Iizuka T., Ikeda M., Asada K. IEEE transactions on very large scale integration (VLSI) systems . 2007,第6期

机译：通过关键区域最小化来优化产量的时序感知单元布局解压缩
2. Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization [J] . Tetsuya IIZUKA, Makoto IKEDA, Kunihiro ASADA IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 2005,第7期

机译：布线故障最小化的CMOS逻辑单元的良率最优布局合成
3. YOR: a yield-optimizing routing algorithm by minimizing critical areas and vias [J] . Kuo S.-Y. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1993,第9期

机译：YOR：通过最小化关键区域和通孔来优化良率的布线算法
4. Timing-driven cell layout de-compaction for yield optimization by critical area minimization [C] . Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada, 3rd international conference on theory and practice of electronic governance 2009 . 2009

机译：时序驱动的单元布局解压缩，可通过最小化关键区域来优化产量
5. Exact layout area minimization of static CMOS cells. [D] . Maziasz, Robert L. 1991

机译：静态CMOS单元的精确布局面积最小化。
6. Automatic yield-line analysis of slabs using discontinuity layout optimization [O] . Matthew Gilbert, Linwei He, Colin C. Smith, -1

机译：使用不连续布局优化自动进行板的屈服线分析
7. Layout compaction for yield optimization via critical area minimization [O] . Layout Compaction For, Youcef Bourai 2000

机译：布局紧凑，可通过最小化临界面积来优化产量
8. Critical HTR-Test Facility Kahter. A Program for Verification of Theoretical Models and Minimization of Layout and Safety Margins [R] . Drueke, V., Filges, D., Gerwin, H., 1978

机译：关键的HTR测试设施Kahter。理论模型验证与布局和安全边界最小化的程序

Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization

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