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Reduction of Minimum Operating Voltage (VDDmin) of CMOS Logic Circuits with Post-Fabrication Automatically Selective Charge Injection

机译：采用后制造自动选择性电荷注入降低CmOs逻辑电路的最小工作电压（VDDmin）

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Kentaro Honda; Katsuyuki Ikeuchi; Masahiro Nomura; Makoto Takamiya; Takayasu Sakurai;
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年度 2015
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1. Circuit-Level Modeling of SRAM Minimum Operating Voltage Vddmin in the C40 Node [J] . Lorenzo Ciampolini, Siddharth Gupta, Olivier Callen, Journal of Low Power Electronics . 2012,第1期

机译：C40节点中SRAM最低工作电压Vddmin的电路级建模
2. Charge sharing problems in dynamic logic circuits: BiCMOS versus CMOS and a 1.5 V BiCMOS dynamic logic circuit free from charge sharing problems [J] . Kuo J.B., Chiang C.S. IEEE Transactions on Circuits and Systems. 1 . 1995,第11期

机译：动态逻辑电路中的电荷共享问题：BiCMOS与CMOS和1.5 V BiCMOS动态逻辑电路无电荷共享问题
3. Charge sharing problems in dynamic logic circuits: BiCMOS versusCMOS and a 1.5 V BiCMOS dynamic logic circuit free from charge sharingproblems [J] . Kuo J.B., Chiang C.S. IEEE Transactions on Circuits and Systems. I, Regular Papers . 1995,第11期

机译：动态逻辑电路中的电荷共享问题：没有电荷共享问题的BiCMOS vsCMOS和1.5 V BiCMOS动态逻辑电路
4. Reduction of minimum operating voltage (VDDmin) of CMOS logic circuits with post-fabrication automatically selective charge injection [C] . Honda Kentaro, Ikeuchi Katsuyuki, Nomura Masahiro, International Symposium on Low Power Electronics and Design . 2011

机译：预制后自动选择电荷注入降低CMOS逻辑电路的最小工作电压（V DDmin ）
5. Transistor placement algorithm for automatic layout synthesis of CMOS/BiCMOS logic and interface circuits. [D] . Xia, Hongxia. 1994

机译：晶体管放置算法，用于CMOS / BiCMOS逻辑和接口电路的自动布局合成。
6. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications [O] . Yasunori Takeda, Kazuma Hayasaka, Rei Shiwaku, -1

机译：为低压可穿戴传感器应用而优化的超薄印刷有机TFT CMOS逻辑电路的制造
7. Increasing Minimum Operating Voltage (VDDmin) with Number of CMOS Logic Gates and Experimental Verification with up to 1Mega-Stage Ring Oscillators [O] . Taro Niiyama, Zhe Piao, Koichi Ishida, 2015

机译：通过CmOs逻辑门数和最高1兆级环形振荡器的实验验证来提高最小工作电压（VDDmin）

Reduction of Minimum Operating Voltage (VDDmin) of CMOS Logic Circuits with Post-Fabrication Automatically Selective Charge Injection

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