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Floorplan evaluation with timing-driven global wireplanning, pin assignment, and buffer/wire sizing

机译：布局规划评估采用时序驱动的全局布线规划，引脚分配和缓冲器/线缆尺寸

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Christoph Albrecht; Y Andrew B. Kahng; Er Zelikovskyz;
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年度 2014
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2. Timing-Driven Global Routing with Efficient Buffer Insertion [J] . Jingyu XU, Xianlong HONG, Tong JING IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 2005,第11期

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3. Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets [J] . Ruiming Li, Dian Zhou, Jin Liu, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2005,第12期

机译：两针脚网络的功率最佳同时缓冲器插入/定型和导线定型
4. Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing [C] . Christoph Albrecht, Andrew B. Kahng, Ion Mandoiu, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design . 2002

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6. Clinical Variability in Arch Wires: A Preliminary Study Evaluating Mechanical and Surface Characteristics of Two Different Sized Rectangular Stainless Steel Wires [O] . Alessandro Vena, Jason Carey, Hisham Badawi 2007

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Floorplan evaluation with timing-driven global wireplanning, pin assignment, and buffer/wire sizing

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