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A Novel Si-Tunnel FET based SRAM Design for Ultra Low-Power 0.3V VDD Applications

机译：基于si-Tunnel FET的新型sRam设计，适用于超低功耗0.3V VDD应用

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1. Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications [J] . Adam Makosiej, Navneet Gupta, Naga Vakul, Micro & Nano Letters, IET . 2016,第12期

机译：超低泄漏SRAM设计，具有低于32 nm的隧道FET，适用于低待机功耗应用
2. Design and performance analysis of low-power SRAM based on electrostatically doped tunnel CNTFETs [J] . Bala Shashi, Khosla Mamta Journal of Computational Electronics . 2019,第3期

机译：基于静电掺杂隧道CNTFET的低功耗SRAM的设计和性能分析
3. Design and performance analysis of low-power SRAM based on electrostatically doped tunnel CNTFETs [J] . Bala Shashi, Khosla Mamta Journal of Computational Electronics . 2019,第3期

机译：基于静电隧道CNTFET的低功耗SRAM的设计与性能分析
4. A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications [C] . Singh J., Ramakrishnan K., Mookerjea S., Design Automation Conference (ASP-DAC), 2010 . 2010

机译：基于Si-Tunnel FET的新型SRAM设计，适用于超低功耗0.3V VDD应用
5. Design and analysis of low-power SRAMs. [D] . Sharifkhani, Mohammad. 2006

机译：低功耗SRAM的设计和分析。
6. Low-Power RFED Wake-Up Receiver Design for Low-Cost Wireless Sensor Network Applications [O] . David Galante-Sempere, Dailos Ramos-Valido, Sunil Lalchand Khemchandani, 2020

机译：低功耗RFED唤醒接收器设计用于低成本无线传感器网络应用
7. VariationTolerant Ultra Low-Power Heterojunction Tunnel FET SRAM Design [O] . Vinay Saripalli, Suman Datta, Vijaykrishnan Narayanan, 2011

机译：VariationTolerant超低功耗异质结隧道FET sRam设计

A Novel Si-Tunnel FET based SRAM Design for Ultra Low-Power 0.3V VDD Applications

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