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A Virtual 3-D Multipole Accelerated Extractor for VLSI Parasitic Interconnect Capacitance*

机译：用于VLsI寄生互连电容的虚拟3-D多极加速提取器*

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Zhaozhi Yang; Zeyi Wang; Shuzhou Fang;
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1. Fast capacitance extraction of actual 3-D VLSI interconnects using quasi-multiple medium accelerated BEM [J] . Wenjian Yu, Zeyi Wang, Jiangchun Gu IEEE Transactions on Microwave Theory and Techniques . 2003,第1期

机译：使用准多重介质加速BEM快速提取实际3-D VLSI互连的电容
2. A virtual 3-D fast extractor for interconnect capacitance of multiple dielectrics [J] . Zhaozhi Yang, Zeyi Wang Microelectronic Engineering . 2003,第1a2期

机译：虚拟3-D快速提取器，用于互连多个电介质的电容
3. Finite-Element Computation of Sensitivities of Interconnect Parasitic Capacitances to the Process Variation in VLSI [J] . Qu H., Kong L., Xu Y., IEEE Transactions on Magnetics . 2008,第6期

机译：互连寄生电容灵敏度对VLSI中工艺变化的有限元计算
4. A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance [C] . Zhaozhi Yang, Zeyi Wang, Shuzhou Fang, Asia and South Pacific Design Automation Conference . 2001

机译：用于VLSI寄生互连电容的虚拟3-D多极加速提取器
5. A parasitic capacitance extraction method for VLSI interconnect modeling [D] . Dengi, Enis Aykut 1997

机译：用于VLSI互连建模的寄生电容提取方法
6. Quantum Capacitance Extraction for Carbon Nanotube Interconnects [O] . Vidur Parkash, Ashok K Goel 2010

机译：碳纳米管互连的量子电容提取
7. The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance* [O] . J Insong Hou, Zeyi Wang, Xianlong Hong 2014

机译：VLsI互连电容的分层h自适应三维边界元计算*
8. Extraction of MOS VLSI (Very-Large-Scale-Integrated) Circuit Models Including Critical Interconnect Parasitics [R] . Su, S. L. 1987

机译：提取包括关键互连寄生效应的mOs VLsI（超大规模集成）电路模型

A Virtual 3-D Multipole Accelerated Extractor for VLSI Parasitic Interconnect Capacitance*

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