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4.7 A 2.7 Gb/s CDMA-Interconnect Transceiver Chip Set with Multi-Level Signal Data Recovery for Re-configurable VLSI Systems

机译：4.7具有多级信号数据恢复功能的2.7 Gb / s CDma互连收发器芯片组，用于可重配置的VLsI系统

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Zhiwei Xu; Hyunchol Shin; Jongsun Kim; M. Frank Chang; Charles Chien;
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年度 2014
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1. Bidirectional Multimode Fiber Interconnection at Gb/s Data Rates With Monolithically Integrated VCSEL–PIN Transceiver Chips [J] . Kern A., Paul S., Schwarz W., Photonics Technology Letters, IEEE . 2011,第15期

机译：采用单片集成VCSEL-PIN收发器芯片的Gb / s数据速率的双向多模光纤互连
2. Bidirectional Optical Interconnection at Gb/s Data Rates With Monolithically Integrated VCSEL-MSM Transceiver Chips [J] . Stach M., Rinaldi F., Chandran M., IEEE Photonics Technology Letters . 2006,第期

机译：单片集成VCSEL-MSM收发器芯片以Gb / s数据速率进行双向光互连
3. An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics [J] . Yoshikawa T., Hirata T., Ebuchi T., IEEE transactions on very large scale integration (VLSI) systems . 2008,第9期

机译：用于集成到消费电子产品大型系统级芯片中的1Gb / s以上收发器内核
4. A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems [C] . Zhiwei Xu, Hyunchol Shin, Jongsun Kim, . 2003

机译：2.7 Gb / s CDMA互连收发器芯片组，具有可重新配置的VLSI系统的多级信号数据恢复
5. A mixed-signal self-calibration technique for baseband filters in system-on-chip mobile transceivers. [D] . Choi, Yongsuk. 2014

机译：片上系统移动收发器中基带滤波器的混合信号自校准技术。
6. A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification [O] . Wei He, Jinguo Huang, Tengxiao Wang, 2020

机译：一种高速低成本VLSI系统能够用于动态视觉传感器数据分类的片上在线学习
7. Second Generation 60-GHz Transceiver Chipset Supporting Multiple Modulations at Gb/s data rates (Invited) [O] . Scott Reynolds, Alberto Valdes-garcia, Brian Floyd, 2014

机译：第二代60GHz收发器芯片组支持Gb / s数据速率的多个调制（特邀）

4.7 A 2.7 Gb/s CDMA-Interconnect Transceiver Chip Set with Multi-Level Signal Data Recovery for Re-configurable VLSI Systems

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