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Digital Signal Processing with General Purpose Microprocessors, DSP and Reconfigurable Logic

机译：采用通用微处理器，Dsp和可重构逻辑的数字信号处理

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Sergej Sawitzki; Achim Gratz; Rainer G. Spallek;
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1. Teaching Microprocessors, Microcontrollers, and Digital Signal Processing Courses Using Only One Target Processor: The Newborn dsPIC30F™ from Microchip™ [J] . YASSER MOHANNA, MOSTAFA HAMAD, RABIH JABR, Computer applications in engineering education . 2007,第2期

机译：仅使用一个目标处理器来教授微处理器，微控制器和数字信号处理课程：Microchip™的新生儿dsPIC30F™
2. Automatic unit delay execution circuit for digital signal processing systems based on general-purpose microprocessors [J] . Skodras A.N., Zigouris E. Electronics Letters . 1988,第8期

机译：基于通用微处理器的数字信号处理系统自动单位延迟执行电路
3. Field Programmable DSP Arrays - A Novel Reconfigurable Architecture for Efficient Reliazation of Digital Signal Processing Functions [J] . Amitabha Sinha, Soumojit Acharyya, Suranjan Chakraborty, Signal & Image Processing : An International Journal (SIPIJ) . 2013,第2期

机译：现场可编程DSP阵列-一种有效重构数字信号处理功能的新型可重构架构
4. THE DESIGN AND IMPLEMENTATION OF A CCITT V.32 MODEM ON A GENERAL PURPOSE DIGITAL SIGNAL PROCESSING MICROPROCESSOR [C] . ZHONGMIN LIANG, JUN WANG, YE SHI, IEEE(Institute of Electrical and Electronics Engineers) International Conference on Communications;ICC'87 . 1987

机译：通用数字信号处理微处理机CCITT V.32调制解调器的设计与实现
5. Study on DSP algorithm implementation techniques and memory access reduction for DSP algorithm implementation on Digital Signal Processor. [D] . Liu, Xiangyang. 2010

机译：研究DSP算法实现技术和数字信号处理器上DSP算法实现的内存访问减少。
6. Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems [O] . Minsoung Rhee, Mark A. Burns -1

机译：微流控气动逻辑电路和数字微处理器的气动综合微流体系统
7. Field Programmable DSP Arrays - A Novel Reconfigurable Architecture for Efficient Realization of Digital Signal Processing Functions [O] . Sinha, Amitabha, Acharyya, Soumojit, Chakraborty, Suranjan, 2013

机译：现场可编程Dsp阵列 - 一种新的可重构架构数字信号处理功能的有效实现

Digital Signal Processing with General Purpose Microprocessors, DSP and Reconfigurable Logic

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