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An architecture-driven metric for simultaneous placement and global routing for FPGAs

机译：用于FpGa同步放置和全局布线的体系结构驱动度量

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Yao-wen Chang; Yu-tsang Changy;
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年度 2000
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1. Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs [J] . Togawa N., Yanagisawa M. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1998,第9期

机译：Maple-opt：面向FPGA的面向性能的同步技术映射，布局和全局路由算法
2. A Performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs [J] . Nozomu TOGAWA, Masao SATO, Tatsuo OHTSUKI IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 1997,第10期

机译：面向性能的同时处理和全局布线算法，用于传输处理FPGA
3. Performance-driven simultaneous placement and routing for FPGA's [J] . Nag S.K., Rutenbar R.A. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1998,第6期

机译：性能驱动的FPGA的同时放置和布线
4. An architecture-driven metric for simultaneous placement and global routing for FPGAs [C] . Yao-Wen Chang, Yu-Tsang Chang Conference on Design automation . 2000

机译：由架构驱动的指标，用于FPGA的同时放置和全局布线
5. Performance-driven simultaneous place and route for FPGAs. [D] . Nag, Sudip Kumar. 1995

机译：性能驱动的FPGA同时布局和布线。
6. FPGA-based RF interference reduction techniques for simultaneous PET–MRI [O] . P Gebhardt, J Wehner, B Weissler, -1

机译：基于FPGA的射频干扰减少技术可同时进行PET-MRI
7. An Architecture-Driven Metric for Simultaneous Placement and GlobalRouting for FPGAs [O] . 2008

机译：FPGA的同时布局和全局路由的架构驱动指标

An architecture-driven metric for simultaneous placement and global routing for FPGAs

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