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Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60 Power Saving in Clock Distribution

机译：具有降低争用的半VDD时钟摆动触发器，可在时钟分配中节省高达60％的功耗

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David Levacq; Muhammad Yazid; Hiroshi Kawaguchi; Makoto Takamiya; Takayasu Sakurai;
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1. A reduced clock-swing flip-flop (RCSFF) for 63% power reduction [J] . Kawaguchi H., Sakurai T. IEEE Journal of Solid-State Circuits . 1998,第5期

机译：减少了时钟摆幅触发器（RCSFF），功耗降低了63％
2. A reduced clock-swing flip-flop (RCSFF) for 63% power reduction [J] . Kawaguchi H., Sakurai T. IEEE Journal of Solid-State Circuits . 1998,第5期

机译：减少了时钟摆幅触发器（RCSFF），功耗降低了63％
3. Low-Power High-Speed Reduced-Clock-Swing Flip-Flops Based on Contention Reduction Techniques [J] . Muhammad Yazid, Hiroshi Kawaguchi, Takayasu Sakurai 電子情報通信学会技術研究報告. 集積回路. Integrated Circuits and Devices . 2005,第476期

机译：基于竞争减少技术的低功耗高速降时钟摆触发器
4. Half V{sub}(DD) Clock-Swing Flip-Flop with Reduced Contention for up to 60 Power Saving in Clock Distribution [C] . David Levacq, Muhammad Yazid, Hiroshi Kawaguchi, European Solid-State Circuits Conference . 2007

机译：半v {sub}（DD）时钟 - 摆动触发器，减少了争用高达60％的时钟分布省电
5. A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications. [D] . Pontikakis, Bill. 2003

机译：一种新颖的双边沿触发脉冲时钟TSPC D触发器，适用于高性能和低功耗VLSI设计应用。
6. Are the stray 60-Hz electromagnetic fields associated with the distribution and use of electric power a significant cause of cancer? [O] . J D Jackson 1992

机译：与电源分配和使用相关的60 Hz杂散电磁场是否是导致癌症的重要原因？
7. Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS [O] . Yunpeng Cai, Anand Savanth, Pranay Prabhat, 2019

机译：超低功耗18晶体管在65-NM CMOS中完全静态争用单相时钟触发器

Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60 Power Saving in Clock Distribution

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