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Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC

机译：校准和测试数字校准流水线aDC的时间减少技术

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Hsiu-ming (sherman Chang; Chin-hsuan Chen; Kuan-yu Lin; Kwang-ting (tim Cheng;
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年度 2015
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1. Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study [J] . Hsiu-Ming (Sherman) Chang, Kuan-Yu Lin, Kwang-Ting (Tim) Cheng Journal of Electronic Testing: Theory and Applications: Theory and Applications . 2010,第1期

机译：用于数字校准设计的校准和测试时间减少技术：ADC案例研究
2. Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study [J] . Hsiu-Ming Sherman Chang, Kuan-Yu Lin, Kwang-Ting Tim Cheng Journal of Electronic Testing . 2010,第1期

机译：用于数字校准设计的校准和测试时间减少技术：ADC案例研究
3. Tester-Assisted Calibration and Screening for Digitally-Calibrated ADCs [J] . Chang H.-M., Lin K.-Y., Cheng K.-T. Circuits and Systems I: Regular Papers, IEEE Transactions on . 2011,第12期

机译：测试人员辅助的数字校准ADC的校准和筛选
4. Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC [C] . Hsiu-Ming Chang, Chin-Hsuan Chen, Kuan-Yu Lin, VLSI Test Symposium, 2009. VTS '09 . 2009

机译：数字校准流水线ADC的校准和测试时间减少技术
5. Power reduction techniques for CMOS current mode pipelined ADCs. [D] . Chan, Chi Hong. 2007

机译：CMOS电流模式流水线ADC的功耗降低技术。
6. Histogram-Based Calibration Method for Pipeline ADCs [O] . Hyeonuk Son, Jaewon Jang, Heetae Kim, -1

机译：基于直方图的管道ADC校准方法
7. Background Digital Calibration Techniques for Pipelined ADC’s [O] . 2008

机译：用于流水线ADC的背景数字校准技术
8. Radiation Hardening Technique for the Background Calibration of High-Resolution Time-Interleaved ADCs. [R] . Zanchi, A., Katoozi, M. 2017

机译：高分辨率时间交织aDC背景校准的辐射强化技术。

Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC

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