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Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures

机译：通过块结构指令集架构提高指令获取率

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Eric Hao; Po-yung Chang; Marks Evers; Yale N. Patt;
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年度 1997
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3. An Evaluation Framework and Instruction Set Architecture for Ion-Trap based Quantum Micro-architectures [J] . Steven Balensiefer, Lucas Kregor-Stickles, Mark Oskin Computer architecture news . 2005,第2期

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4. Increasing the instruction fetch rate via block-structured instruction set architectures [C] . Eric Hao, Po-Yung Chang, Marius Evers, Annual ACM/IEEE international symposium on Microarchitecture;ACM/IEEE international symposium on Microarchitecture . 1996

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5. Improving instruction fetch rate with code pattern cache for superscalar architecture [D] . Beg, Azam Muhammad 2005

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6. Understanding Evolutionary Potential in Virtual CPU Instruction Set Architectures [O] . David M. Bryson, Charles Ofria -1

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7. Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache [O] . 2008

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8. Evaluation of DOD Comments Re: 'DOD Instruction 5000.5X, Standard Instruction Set Architectures for Embedded Computers. [R] . 1982

机译：评估DOD评论Re：'DOD指令5000.5X，嵌入式计算机的标准指令集架构。

Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures

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