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Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator

机译：为isCsI Initiator设计千兆位硬件加速器

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2. Efficiency Versus Accuracy: A Review of Design Techniques for DNN Hardware Accelerators [J] . Cecilia Latotzke, Tobias Gemmeke Quality Control, Transactions . 2021,第1期

机译：效率与准确性：DNN硬件加速器设计技术综述
3. Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators [J] . Xu Siyuan, Liu Shuangnan, Liu Yidi, Microprocessors and microsystems . 2019,第MARa期

机译：具有可变数量的硬件加速器的异构MPSoC的设计空间探索
4. Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator [C] . Chung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, IEEE Conference on Local Computer Networks . 2006

机译：iSCSI发起者的GIGA位硬件加速器设计
5. Design and Generation of Efficient Hardware Accelerators for Sparse and Dense Tensor Computations [D] . ?Srivastava, Nitish Kumar 2020

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6. Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators Using Time Compression Supporting Multiple Spike Codes [O] . Changqing Xu, Wenrui Zhang, Yu Liu, 2020

机译：使用时间压缩支撑多穗码的硬件尖峰神经加速器的吞吐量和效率
7. Efficiency Versus Accuracy: A Review of Design Techniques for DNN Hardware Accelerators [O] . Cecilia Latotzke, Tobias Gemmeke 2021

机译：效率与准确性：DNN硬件加速器设计技术综述

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