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MUTE-AES: A Multiprocessor Architecture to prevent Power Analysis based Side Channel Attack of the AES Algorithm

机译：mUTE-aEs：一种多处理器架构，用于防止aEs算法的基于功率分析的侧信道攻击

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Jude Angelo Ambrose; Sri Parameswaran; Ar Ignjatovic;
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年度 2014
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1. Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks [J] . Ambrose J.A., Ragel R.G., Parameswaran S., Computers & Digital Techniques, IET . 2011,第1期

机译：多处理器信息隐藏架构可防止基于功率分析的边信道攻击
2. Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks [J] . Circuits, Devices & Systems, IET . 2013,第5期

机译：随机的多模残数加倍系统架构，可防止功率分析副信道攻击
3. AES-Based Security Coprocessor IC in 0.18-μm CMOS With Resistance to Differential Power Analysis Side-Channel Attacks [J] . David D. Hwang, Kris Tiri, Alireza Hodjat, IEEE Journal of Solid-State Circuits . 2006,第4期

机译：0.18μmCMOS中基于AES的安全协处理器IC，可抵抗差分功率分析侧通道攻击
4. MUTE-AES: A multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm [C] . Ambrose Jude Angelo, Parameswaran Sri, Ignjatovic Aleksandar IEEE/ACM International Conference on Computer-Aided Design . 2008

机译：MUTE-AES：一种多处理器架构，用于防止基于功率分析的AES算法的侧频攻击
5. A Novel and Cost-Effective Test Bed Implementation of Side Channel Attacks on Aes: Leveraging Correlation Power Analysis and Machine Learning. [D] . Adegbite, Oluwadara John. 2017

机译：一种对Aes进行边信道攻击的新颖且经济高效的测试平台实施方案：利用相关功率分析和机器学习。
6. Secure Trust-Based Blockchain Architecture to Prevent Attacks in VANET [O] . Adnan Shahid Khan, Kuhanraj Balan, Yasir Javed, 2019

机译：安全的基于信任的区块链架构可防止VANET中的攻击
7. AES-Based Security Coprocessor IC in 0.18-um CMOS with Resistance to Differential Power Analysis Side-Channel Attacks [O] . Hwang DD, Tiri K, Hodjat A, 2006

机译：0.18um CMOS中基于AES的安全协处理器IC，可抵抗差分功率分析侧通道攻击
8. Algorithm-Based Low-Power Transform Coding Architectures. Part 2. Logarithmic Complexity, Unified Architecture, and Finite-Precision Analysis. [R] . Wu, A., Liu, K. J. 1995

机译：基于算法的低功耗变换编码体系结构。第2部分。对数复杂性，统一架构和有限精度分析。

MUTE-AES: A Multiprocessor Architecture to prevent Power Analysis based Side Channel Attack of the AES Algorithm

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