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Spatial Memoization: Concurrent Instruction Reuse to Correct Timing Errors in SIMD Architectures

机译：空间记忆：并发指令重用以纠正sImD架构中的时序错误

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Abbas Rahimi; Student Member; Luca Benini; Rajesh K. Gupta;
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年度 2014
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1. Spatial Memoization: Concurrent Instruction Reuse to Correct Timing Errors in SIMD Architectures [J] . Rahimi A., Benini L., Gupta R.K. Circuits and Systems II: Express Briefs, IEEE Transactions on . 2013,第12期

机译：空间记忆化：并发指令重用以纠正SIMD架构中的时序错误
2. Lane Decoupling for Improving the Timing-Error Resiliency of Wide-SIMD Architectures [J] . Evgeni Krimer, Patrick Chiang, Mattan Erez Computer architecture news . 2012,第3期

机译：通道解耦，以提高宽SIMD架构的时序误差弹性
3. A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy [J] . Chao YAN, Hongjun DAI, Tianzhou CHEN IEICE transactions on information and systems . 2012,第1期

机译：具有用于指令级时间冗余的纠错码的容错架构
4. Look It Up or Do the Math: An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization [C] . Daniel Citron, Dror G. Feitelson International Workshop on Power-Aware Computer Systems(PACS 2003) . 2004

机译：查看或进行数学：指令重用和备忘的能量，区域和时序分析
5. ILP-SIMD: An instruction parallel SIMD architecture with short -wire interconnects. [D] . Chung, Kee Shik. 2000

机译：ILP-SIMD：具有短线互连的指令并行SIMD体系结构。
6. A Spatial Control for Correct Timing of Gene Expression during the Escherichia coli Cell Cycle [O] . Yuan Yao, Lifei Fan, Yixin Shi, 2017

机译：大肠杆菌细胞周期中基因表达的正确时机的空间控制。
7. Lane Decoupling for Improving the Timing-Error Resiliency of Wide-SIMD Architectures [O] . Evgeni Krimer, Patrick Chiang, Mattan Erez 2013

机译：用于提高宽sImD架构的定时误差弹性的通道解耦

Spatial Memoization: Concurrent Instruction Reuse to Correct Timing Errors in SIMD Architectures

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