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An All-Digital, Highly Scalable Architecture for Measurement of Spatial Variation in Digital Circuits

机译：用于测量数字电路空间变化的全数字，高度可扩展架构

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Nigel Drego; Anantha Ch; Duane Boning;
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1. All-Digital Circuits for Measurement of Spatial Variation in Digital Circuits [J] . Drego N., Chandrakasan A., Boning D. Solid-State Circuits, IEEE Journal of . 2010,第3期

机译：用于测量数字电路中空间变化的全数字电路
2. An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience [J] . Chou Pei-Yuan, Wang Jinn-Shyan IEEE transactions on circuits and systems . I , Regular papers . 2019,第7期

机译：具有自动分辨率校准功能的全数字片上峰峰值抖动测量电路，可实现高PVT变化弹性
3. An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits [J] . Huang Y.-C., Wang P.-Y., Liu S.-I. Circuits and Systems II: Express Briefs, IEEE Transactions on . 2012,第3期

机译：CDR电路的全数字抖动容限测量技术
4. An all-digital, highly scalable architecture for measurement of spatial variation in digital circuits [C] . Drego Nigel, Chandrakasan Anantha, Boning Duane IEEE Asian Solid-State Circuits Conference . 2008

机译：一种用于测量数字电路空间变化的全数字高度可扩展的架构
5. Scalable Digital Architecture of Hierarchical Temporal Memory Spatial Pooler [D] . Praveen, Sadhvi. 2017

机译：分层时间记忆空间池的可扩展数字体系结构
6. A Digital Model to Simulate Effects of Bone Architecture Variations on Texture at Spatial Resolutions of CT HR-pQCT and μCT Scanners [O] . T. Lowitz, O. Museyko, V. Bousson, 2014

机译：在CTHR-pQCT和μCT扫描仪的空间分辨率下模拟骨骼结构变化对纹理的影响的数字模型
7. All-Digital Circuits for Measurement of Spatial Variation in Digital Circuits [O] . Nigel Drego, Anantha Chandrakasan, Duane Boning 2010

机译：用于测量数字电路空间变化的全数字电路

An All-Digital, Highly Scalable Architecture for Measurement of Spatial Variation in Digital Circuits

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