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Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits+

机译：内置生成的同步时序电路加权测试序列+

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Sudhakar Reddy; See Profile; Irith Pomeranz; Sudhakar M. Reddy;
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年度 2000
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专利

1. Application of homing sequences to synchronous sequential circuit testing [J] . Pomeranz I., Reddy S.M. IEEE Transactions on Computers . 1994,第5期

机译：归位序列在同步时序电路测试中的应用
2. Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding [J] . Dong Xiang, Xiaoqing Wen, Laung-Terng Wang IEEE transactions on very large scale integration (VLSI) systems . 2017,第3期

机译：基于加权伪随机测试码型生成和重播的基于低功耗扫描的内置自测
3. Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits [J] . Pomeranz I., Reddy S.M. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2006,第6期

机译：透明DFT：针对同步时序电路的可测试性和测试生成方法的设计
4. Built-in generation of weighted test sequences for synchronous sequential circuits [C] . Irith Pomeranz, Sudhakar M. Reddy, PIrith Pomeranz, Annual Workshop on Petascale Data Storage;Workshop on Petascale Data Storage . 2009

机译：内置生成同步时序电路的加权测试序列
5. AN HEURISTIC SEARCH APPROACH TO TEST SEQUENCE GENERATION FOR AHPL (A HARDWARE PROGRAMMING LANGUAGE) DESCRIBED SYNCHRONOUS SEQUENTIAL CIRCUITS, [D] . BELT, JOHN EDWARD. 1973

机译：一种针对AHPL（硬件编程语言）描述的同步顺序电路的测试序列生成的启发式搜索方法，
6. Flexibly Monitoring Group Sequential Survival Trials When Testing is Based Upon a Weighted Log-Rank Statistic [O] . Sean S. Brummel, Daniel L. Gillen -1

机译：当测试基于加权对数秩统计时可以灵活地监视组顺序生存试验
7. Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits [O] . Irith Pomeranz And 2000

机译：内置一代同步时序电路的加权测试序列
8. Automatic Test Pattern Generation for Synchronous Sequential Circuits [R] . Konijnenburg, M. H. 1998

机译：同步时序电路的自动测试模式生成

Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits+

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