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Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems

机译：用于片上系统嵌入式系统的power aware外部总线仲裁

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Ke Ning; David Kaeli;
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年度 2008
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1. Latency-Aware Bus Arbitration for Real-Time Embedded Systems [J] . Minje JUN, Kwanhu BANG, Hyuk-Jun LEE, IEICE Transactions on Information and Systems . 2007,第3期

机译：实时嵌入式系统的延迟感知总线仲裁
2. POWER-AWARE BUS ENCODING TECHNIQUES FOR I/O AND DATA BUSES IN AN EMBEDDED SYSTEM [J] . WEI-CHUNG CHENG, MASSOUD PEDRAM Journal of Circuits, Systems, and Computers . 2002,第4期

机译：嵌入式系统中I / O和数据总线的Power-Aware总线编码技术
3. Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment [J] . Rau J.-C., Wu P.-H. Computers & Digital Techniques, IET . 2011,第1期

机译：低成本环境中片上系统的功率感知多链编码方案
4. Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems [C] . Ke Ning, David Kaeli International Conference on High Performance Embedded Architectures and Compilers(HiPEAC 2005); 20051117-18; Barcelona(ES) . 2005

机译：片上系统嵌入式系统的电源感知外部总线仲裁
5. A unified hardware-software framework for evaluating power consumption of embedded system-on-a-chip designs. [D] . Talarico, Claudio. 2004

机译：一个用于评估嵌入式片上系统设计功耗的统一硬件软件框架。
6. An Inductively Powered Scalable 32-Channel Wireless Neural Recording System-on-a-Chip for Neuroscience Applications [O] . Seung Bae Lee, Hyung-Min Lee, Mehdi Kiani, -1

机译：感应供电可扩展的32通道无线神经记录系统芯片为神经科学应用
7. Evaluating Power Consumption of Parameterized Cache and Bus Architectures in System-on-a-Chip Designs [O] . Tony Givargis, Frank Vahid, Jörg Henkel, 2001

机译：评估片上系统设计中参数化缓存和总线体系结构的功耗

Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems

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