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Nano Scale Single and Double Gate SOI MOSFETs Structures and Compression of Electrical Performance Factors

机译：纳米级单和双栅sOI mOsFET结构和电气性能因子压缩

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Indra Vijay Singh; M. S Alam;
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年度 2011
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1. Study of performance and leakage currents in nanometer-scale bulk, SOI and double-gate MOSFETs [J] . Sudarshan Narayanan, C. Sachs, M.V. Fischetti Journal of Computational Electronics . 2008,第1期

机译：研究纳米级体，SOI和双栅极MOSFET中的性能和泄漏电流
2. Performance Analysis of Electrical Characteristics of Single Gate and Double Gate Nano-MOSFET Devices [J] . G.S.M Galadanci, Abdulrazak Tijjani, Sulaimanmuhammad Gana American Journal of Engineering Research . 2018,第6期

机译：单门和双栅极纳米MOSFET器件电特性的性能分析
3. Analog/RF Performance Investigation of Nanoscale Gate-Underlap Single and Double Gate Silicon-On-Insulator MOSFETs with High-k Stack on Spacer [J] . Singh Indra Vijay, Alam M. S. Journal of Nanoelectronics and Optoelectronics . 2015,第6期

机译：间隔器上具有高k堆栈的纳米级栅下单层和双栅绝缘体上硅MOSFET的模拟/ RF性能研究
4. Investigation of single and double gate SOI MOSFETs in Accumulation Mode for enhanced performances and reduced technological drawbacks [C] . E. Rauly, B. Iniguez, D. Flandre, European solid-state device research conference . 2000

机译：累积模式中单栅极SOI MOSFET的研究，提高性能和减少技术缺点
5. Scaling limits and opportunities of double-gate MOSFETs. [D] . Chen, Qiang. 2003

机译：双栅极MOSFET的扩展极限和机会。
6. Performance of arsenene and antimonene double-gate MOSFETs from first principles [O] . Giovanni Pizzi, Marco Gibertini, Elias Dib, -1

机译：首要原理的砷和锑双栅极MOSFET的性能
7. Double-Gate Fully-Depleted SOI Transistors for Low-Power High-Performance Nano-Scale Circuit Design [O] . Rongtian Zhang, Kaushik Roy, David B. Janes 2013

机译：用于低功耗高性能纳米级电路设计的双栅极全耗尽SOI晶体管

Nano Scale Single and Double Gate SOI MOSFETs Structures and Compression of Electrical Performance Factors

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