首页> 外文OA文献 >An integrated flow for the design of hardened circuits on SRAM-based FPGAs

【2h】

An integrated flow for the design of hardened circuits on SRAM-based FPGAs

机译：在基于sRam的FpGa上设计硬化电路的集成流程

页面导航

著录项
引文网络
相似文献
相关主题

著录项

作者
Cristiana Bolchini; Antonio Miele; Chiara S; Niccolò Battezzati; Luca Sterpone; Massimo Violante;
展开▼
作者单位

展开▼
年度 2011
总页数
原文格式 PDF
正文语种
中图分类

相似文献

外文文献
中文文献
专利

1. Design and Characterization of SEU Hardened Circuits for SRAM-Based FPGA [J] . Li Tianwen, Liu Hongjin, Yang Haigang IEEE transactions on very large scale integration (VLSI) systems . 2019,第6期

机译：基于SRAM的SEU硬化电路的设计与表征
2. Design and Characterization of SEU Hardened Circuits for SRAM-Based FPGA [J] . Li Tianwen, Liu Hongjin, Yang Haigang IEEE transactions on very large scale integration (VLSI) systems . 2019,第6期

机译：SRAM基于SRAM的FPGA的SEU硬化电路的设计与表征
3. Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs [J] . Anees Ullah, Luca Sterpone Journal of Electronic Testing: Theory and Applications: Theory and Applications . 2014,第4期

机译：基于SRAM的FPGA上映射的电路的恢复时间和容错能力的提高
4. An integrated flow for the design of hardened circuits on SRAM-based FPGAs [C] . Bolchini Cristiana, Miele Antonio, Sandionigi Chiara, 2010 15th IEEE European Test Symposium . 2010

机译：在基于SRAM的FPGA上设计强化电路的集成流程
5. AN APPROACH TO THE DESIGN OF RELIABLE RADIATION HARDENED INTEGRATED LOGICAND SEQUENTIAL CIRCUITS. [D] . MAURER, HAROLD EUGENE. 1965

机译：一种可靠的辐射硬化集成逻辑顺序电路的设计方法。
6. Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad [O] . Changyeop Lee, Gyuseong Cho, Troy Unruh, 2020

机译：用于辐射硬化电荷敏感放大器的集成电路设计最多2个MRAD
7. An integrated flow for the design of hardened circuits on SRAM-based FPGAs [O] . Bolchini C., Miele A., Sandionigi C., 2010

机译：在基于SRAM的FPGA上设计强化电路的集成流程

An integrated flow for the design of hardened circuits on SRAM-based FPGAs

著录项

引文网络

相似文献

相关主题

期刊订阅