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Paceline: Improving single-thread performance in nanoscale CMPs through core overclocking

机译：paceline：通过核心超频提高纳米级Cmp的单线性能

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Brian Greskamp; Josep Torrellas;
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年度 2007
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1. From Hyperbranched Polymer to Nanoscale CMP (NCMP): Improved Microscopic Porosity, Enhanced Light Harvesting, and Enabled Solution Processing into White-Emitting Dye@NCMP Films [J] . Peng Zhang, Keyi Wu, Jia Guo ACS Macro Letters . 2014,第11期

机译：从超支化聚合物到纳米级CMP（NCMP）：改进的微观孔隙率，增强的光收集能力以及将溶液加工成发白染料@NCMP膜的能力
2. Boosting Single-thread Performance in Multi-core Systems through Fine-Grain Multi-Threading [J] . Carlos Madriles, Pedro Lopez, Josep M. Codina, Computer architecture news . 2009,第3期

机译：通过细粒度多线程提高多核系统中的单线程性能
3. Achieving Predictable Performance through Better Memory Controller Placement in Many-Core CMPs [J] . Dennis Abts, Natalie D. Enright Jerger, John Kim, Computer architecture news . 2009,第3期

机译：通过在多核CMP中更好地放置内存控制器来实现可预测的性能
4. Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking [C] . Greskamp, Brian, Torrellas, . 2007

机译：Paceline：通过核心超频提高纳米级CMP的单线程性能
5. Energy efficient load latency tolerance: Single-thread performance for the multi-core era. [D] . Hilton, Andrew D. 2010

机译：节能高效的负载延迟容忍度：多核时代的单线程性能。
6. Formation polarity dependent improved resistive switching memory characteristics using nanoscale (1.3 nm) core-shell IrOx nano-dots [O] . Writam Banerjee, Siddheswar Maikap, Chao-Sung Lai, 2012

机译：使用纳米级（1.3 nm）核-壳IrOx纳米点的依赖于形成极性的改进的电阻开关存储特性
7. Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications [O] . Keita Doi, Ryota Shioya, Hideki Ando 2018

机译：用于单线程应用的紧密耦合多核架构中的性能改进技术

Paceline: Improving single-thread performance in nanoscale CMPs through core overclocking

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