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Instruction Prefetching of Systems Codes With Layout Optimized for Reduced Cache Misses

机译：具有针对减少高速缓存未命中优化的布局的系统代码的指令预取

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Chun Xia; Josep Torrellas;
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年度 1996
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1. Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches through Programmable Decoders [J] . Chuanjun Zhang Computer architecture news . 2006,第2期

机译：平衡缓存：通过可编程解码器减少直接映射缓存的冲突丢失
2. Fast indexing for blocked array layouts to reduce cache misses [J] . Evangelia Athanasaki, Nectarios Koziris International Journal of High Performance Computing and Networking . 2005,第5a6期

机译：快速索引以阻塞阵列的布局，以减少缓存未命中
3. Refactoring Intermediately Executed Code to Reduce Cache Capacity Misses [J] . Kristof Beyls, Erik H. DHollander Journal of instruction-level parallelism . 2008,第2008期

机译：重构中间执行的代码以减少高速缓存容量丢失
4. Instruction prefetching of systems codes with layout optimized for reduced cache misses [C] . Chun Xia, Josep Torrellas Annual international symposium on Computer architecture;International symposium on Computer architecture . 1996

机译：通过优化布局以减少高速缓存未命中的指令对系统代码进行预取
5. Code layout optimization for remote progressive code update for networked embedded systems. [D] . Kim, Jinsik. 2010

机译：用于网络嵌入式系统的远程渐进式代码更新的代码布局优化。
6. Combining Instruction Prefetching with Partial Cache Locking to Improve WCET in Real-Time Systems [O] . Fan Ni, Xiang Long, Han Wan, -1

机译：将指令预取与部分缓存锁定相结合以改善实时系统中的WCET
7. Balanced Instruction Cache: Reducing Conflict Misses of Direct- Mapped Caches through Balanced Subarray Accesses [O] . 2008

机译：平衡指令高速缓存：通过平衡子阵列访问减少直接映射高速缓存的冲突未命中

Instruction Prefetching of Systems Codes With Layout Optimized for Reduced Cache Misses

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