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A Compact High-Speed (31,5) Parallel Counter Circuit Based on Capacitive Threshold-Logic Gates

机译：基于电容门限逻辑门的紧凑型高速（31,5）并行计数器电路

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Y. Leblebici; H. Özdemir; A. Kepkep; U. Çilingiroglu; U. Cilingiro Glu;
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年度 1996
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1. A compact high-speed (31,5) parallel counter circuit based on capacitive threshold-logic gates [J] . Leblebici Y., Ozdemir H. IEEE Journal of Solid-State Circuits . 1996,第8期

机译：基于电容性阈值逻辑门的紧凑型高速（31,5）并行计数器电路
2. A Balanced Capacitive Threshold-Logic Gate [J] . JAVIER LOPEZ-GARCIA, JOSE FERNANDEZ-RAMOS, ALFONSO GAGO-BOHORQUEZ Analog Integrated Circuits and Signal Processing . 2004,第1期

机译：平衡电容阈值逻辑门
3. A capacitive threshold-logic gate [J] . Ozdemir H., Kepkep A. IEEE Journal of Solid-State Circuits . 1996,第8期

机译：电容阈值逻辑门
4. A Compact Parallel (31,5)-Counter Circuit Based on Capacitive Threshold-Logic Gates [C] . Leblebici Y., Ozdemir H., Kepkep A., Twenty-First Solid-State Circuits Conference (ESSCIRC '95) . 1995

机译：基于电容阈值逻辑门的紧凑型并行（31,5）-计数器电路
5. Inductive and capacitive aware methodologies for physical and circuit synthesis of high-speed digital and RF circuits. [D] . Bhaduri, Amitava. 2005

机译：用于高速数字和RF电路的物理和电路综合的感应和电容感知方法。
6. On Frequency-Based Interface Circuits for Capacitive MEMS Accelerometers [O] . Zhiliang Qiao, Boris A. Boom, Anne-Johan Annema, 2018

机译：电容式MEMS加速度计的基于频率的接口电路
7. The noise performance of a high-speed capacitive-sensor interface based on a relaxation oscillator and a fast counter [O] . Gasulla Forner, Manuel, Li, Xiujun, Meijer, Gerard C. M. 2005

机译：基于张弛振荡器和快速计数器的高速电容传感器接口的噪声性能
8. EFFICIENT MODELING OF INTERCONNECTS AND CAPACITIVE DISCONTINUITIES IN HIGH-SPEED DIGITAL CIRCUITS [R] . K. S. Oh, J. Schutt-Aine 1995

机译：高速数字电路中互连和电容不连续的有效建模

A Compact High-Speed (31,5) Parallel Counter Circuit Based on Capacitive Threshold-Logic Gates

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