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Gate dielectric scaling for high-performance CMOS: from SiO2 to High-K

机译：用于高性能CmOs的栅极介电缩放：从siO2到High-K

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Robert Chau; Suman Datta; Mark Doczy; Jack Kavalieros; Matthew Metz;
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年度 2004
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1. Improvement of metal gate/high-K dielectric CMOSFETs characteristics by atomic layer etching of high-K gate dielectric [J] . K.S. Min, C. Park, C.Y. Kang, Solid-State Electronics . 2013,第apra期

机译：通过对高K栅极电介质进行原子层蚀刻来改善金属栅极/高K电介质CMOSFET的特性
2. The Effects of Chemical Bonding and Band Offset Constraints at Si-Dielectric Interfaces on the Integration of Alternative High-K Dielectrics into Aggressively-Scaled CMOS Si Devices [J] . Gerald Lucovsky, James C. Phillips Microelectronic Engineering . 1999,第1a4期

机译：Si-电介质界面处的化学键合和能带偏移约束对替代性高K电介质集成到积极规模的CMOS Si器件中的影响
3. Scalable, High-Performance Printed InOx Transistors Enabled by Ultraviolet-Annealed Printed High-k AlOx Gate Dielectrics [J] . Scheideler William J., McPhail Matthew W., Kumar Rajan, ACS applied materials & interfaces . 2018,第43期

机译：通过紫外线退火印刷的高k Alox栅极电介质使能可扩展，高性能印刷的内氧管晶体管
4. Gate dielectric scaling for high-performance CMOS: from SiO/sub 2/ to high-K [C] . Chau R., Datta S., Doczy M., Gate Insulator, 2003. IWGI 2003. Extended Abstracts of International Workshop on . 2003

机译：用于高性能CMOS的栅极介电缩放：从SiO / sub 2 /到高K
5. High-permittivity dielectrics and high mobility semiconductors for future scaled technology: Hafnium-based high-K gate dielectrics and interface engineering for hafnium oxide/germanium CMOS device [D] . Lu, Nan 2006

机译：适用于未来规模化技术的高介电常数电介质和高迁移率半导体：氧化ha /锗CMOS器件的Ha基高K栅极电介质和界面工程
6. High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure [O] . Szu-Hung Chen, Wen-Shiang Liao, Hsin-Chia Yang, 2012

机译：具有纳米堆叠的高k栅极电介质和3D鳍形结构的高性能III-V MOSFET
7. Atomic Layer Deposition for CMOS Scaling: High-k Gate Dielectrics on Si, Ge, and III-V Semiconductors [O] . Martin M. Frank 2016

机译：用于CmOs缩放的原子层沉积：si，Ge和III-V半导体上的高k栅介质

Gate dielectric scaling for high-performance CMOS: from SiO2 to High-K

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