首页> 外文OA文献 >Linear Timing Analysis Of Soc Synchronous Circuits With Level-Sensitive Latches

【2h】

Linear Timing Analysis Of Soc Synchronous Circuits With Level-Sensitive Latches

机译：具有电平敏感锁存器的soc同步电路的线性时序分析

页面导航

著录项
引文网络
相似文献
相关主题

著录项

作者
Baris Taskin; Ivan S. Kourtev;
展开▼
作者单位

展开▼
年度 2002
总页数
原文格式 PDF
正文语种
中图分类

相似文献

外文文献
中文文献
专利

1. Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits [J] . Taskin B., Kourtev I.S. IEEE transactions on very large scale integration (VLSI) systems . 2004,第1期

机译：时序分析的线性化和对电平敏感的数字同步电路的优化
2. Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits [J] . Taskin B., Kourtev I.S. IEEE transactions on very large scale integration (VLSI) systems . 2004,第1期

机译：时序分析的线性化和对电平敏感的数字同步电路的优化
3. Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits [J] . Taskin B., Kourtev I.S. IEEE transactions on very large scale integration (VLSI) systems . 2004,第1期

机译：电平敏感数字同步电路定时分析和优化的线性化
4. Linear timing analysis of SOC synchronous circuits with level-sensitive latches [C] . Taskin, B., Kourtev, . 2002

机译：具有电平敏感锁存器的SOC同步电路的线性时序分析
5. Multi-Gigahertz Synchronous Sampling and Triggering (SST) Circuit with Picosecond Timing Resolution [D] . Chiem, Edwin Y. 2017

机译：具有皮秒定时分辨率的多千兆赫同步采样和触发（SST）电路
6. Analysis of complex neural circuits with nonlinear multidimensional hidden state models [O] . Alexander Friedman, Joshua F. Slocum, Danil Tyulmankov, 2016

机译：非线性多维隐藏状态模型对复杂神经电路的分析
7. A Timing Analysis Algorithm for Circuits with Level-Sensitive Latches [O] . 2008

机译：具有电平敏感锁存电路的时序分析算法

Linear Timing Analysis Of Soc Synchronous Circuits With Level-Sensitive Latches

著录项

引文网络

相似文献

相关主题

期刊订阅