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A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits

机译：一种有效估计时序逻辑电路中开关动作的方法

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José Monteiro; Srinivas Devadas; Bill Lin;
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年度 1994
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专利

1. Estimation of average switching activity in combinational logic circuits using symbolic simulation [J] . Monteiro J., Devadas S. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1997,第1期

机译：使用符号仿真估计组合逻辑电路中的平均开关活动
2. Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs [J] . Neeraja Jagadeesan, B. Saman, M. Lingalugari, International Journal of High Speed Electronics and Systems: Devices, Integrated Circuits and Systems, Optical and Quantum Electronics . 2015,第3a4期

机译：使用空间波函数开关（SWS）FET的顺序逻辑电路
3. Methodology for manipulation of Karnaugh maps designing for pneumatic sequential logic circuits [J] . Adriano A. Santos, Antonio Ferreira da Silva International Journal of Mechatronics and Automation . 2017,第1期

机译：用于操纵Karnaugh地图设计气动序列逻辑电路的方法
4. A methodology for efficient estimation of switching activity in sequential logic circuits [C] . Jose Monteiro, Srinivas Devadas, Bill Lin, Annual conference on Design automation;Conference on Design automation . 1994

机译：在顺序逻辑电路中有效估计开关活动的方法
5. An energy efficient design methodology for combinational logic circuits. [D] . Schindler, Kris David. 2001

机译：组合逻辑电路的节能设计方法。
6. Synthesizing a novel genetic sequential logic circuit: a push-on push-off switch [O] . Chunbo Lou, Xili Liu, Ming Ni, 2010

机译：合成新颖的遗传顺序逻辑电路：推入式推压开关
7. Estimation of Average Switching Activity in Combinational and Sequential Circuits [O] . Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer, 1992

机译：组合和时序电路中平均开关活动的估算

A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits

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