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Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-core Co-design

机译：利用分析模型有效探索硬件事务内存和多核协同设计

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James Poe; Chang-burm Cho; Tao Li;
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年度 2008
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1. Power Efficient Hardware Transactional Memory: Dynamic Issue of Transactions [J] . Do Sang Wook Stephen, Dubois Michel ACM Transactions on Architecture and Code Optimization . 2016,第1期

机译：高效的硬件事务存储：事务的动态发布
2. Efficient execution of speculative threads and transactions with hardware transactional memory [J] . Gongming Li, Hong An, Qi Li, Future generation computer systems . 2014,第jana期

机译：利用硬件事务存储器有效执行推测性线程和事务
3. Tokentm: Efficient Execution Of Large Transactions With Hardware Transactional Memory [J] . Jayaram Bobba, Neelam Goyal, Mark D. Hill, Computer architecture news . 2008,第3期

机译：Tokentm：使用硬件事务存储有效执行大事务
4. Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design [C] . Poe James, Cho Chang-Burm, Li Tao International Symposium on Computer Architecture and High Performance Computing . 2008

机译：使用分析模型有效地探索硬件交易记忆和多核共同设计
5. Developing representative workloads for future hardware transactional memory research using a cycle-accurate, multidimensional hardware transactional memory model. [D] . Poe, James Michael, II. 2009

机译：使用周期精确的多维硬件事务存储模型为将来的硬件事务存储研究开发代表性的工作负载。
6. Efficient Synapse Memory Structure for Reconfigurable Digital Neuromorphic Hardware [O] . Jinseok Kim, Jongeun Koo, Taesu Kim, 2018

机译：可重构数字神经形态硬件的高效突触存储器结构
7. Opportunities and pitfalls of multi-core scaling using Hardware Transaction Memory∗ [O] . 2015

机译：使用硬件事务内存进行多核扩展的机会和陷阱*

Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-core Co-design

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