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Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures

机译：缓冲最小化混合CpU / FpGa架构上的实时流应用程序调度

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Jun Zhu; Ingo Sander; Axel Jantsch;
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年度 2009
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1. Application Development with the FlexWAFE Real-Time Stream Processing Architecture for FPGAs [J] . AMILCAR DO CARMO LUCAS, HENNING SAHLBACH, SEAN WHITTY, ACM Transactions on Embedded Computing Systems . 2010,第1期

机译：利用FPGA的FlexWAFE实时流处理架构进行应用开发
2. Genetic algorithms for scheduling in a CPU/FPGA architecture with heterogeneous communication delays [J] . Abdallah Fadel, Tanougast Camel, Kacem Imed, Computers & Industrial Engineering . 2019,第Nova期

机译：具有异构通信延迟的用于在CPU / FPGA架构中进行调度的遗传算法
3. Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays [J] . El Cadi Abdessamad Ait, Souissi Omar, Ben Atitallah Rabie, Journal of Intelligent Manufacturing . 2018,第3期

机译：具有异构通信延迟的CPU / FPGA架构中调度的数学编程模型
4. Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures [C] . Jun Zhu, Sander I., Jantsch A. Design, Automation amp; Test in Europe Conference amp; Exhibition, 2009. DATE '09 . 2009

机译：在混合CPU / FPGA架构上最小化实时流式应用程序调度的缓冲区
5. Extending the thread programming model across CPU and FPGA hybrid architectures. [D] . Jidin, Razali. 2005

机译：跨CPU和FPGA混合架构扩展线程编程模型。
6. Modularized architecture of address generation units suitable for real-time processing MR data on an FPGA [O] . Limin Li, Alice M. Wyrwicz -1

机译：地址生成单元的模块化架构适合在FPGA上实时处理MR数据
7. Efficient Buffer Capacity and Scheduler Setting Computation for Soft Real-Time Stream Processing Applications [O] . Bekooij, Marco, Bekooij, Marco Jan Gerrit, Wiggers, M.H., 2007

机译：用于软实时流处理应用程序的有效缓冲区容量和调度程序设置计算
8. SpaceCubeX: A Framework for Evaluating Hybrid Multi-Core CPU FPGA DSP Architectures. [R] . Schmidt, A. G., Weisz, G., French, M., 2017

机译：spaceCubeX：评估混合多核CpU FpGa Dsp架构的框架。

Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures

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