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Interrupt Costs in Embedded System with Short Latency Hardware Accelerators

机译：具有短延迟硬件加速器的嵌入式系统的中断成本

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Sébastien Lafond; Johan Lilius;
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年度 2007
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1. On Improving Real-Time Interrupt Latencies of Hybrid Operating Systems with Two-Level Hardware Interrupts [J] . Liu Miao, Liu Duo, Wang Yi, Computers, IEEE Transactions on . 2011,第7期

机译：具有两级硬件中断的混合操作系统的实时中断延迟提高
2. Real-Time Apple Detection System Using Embedded Systems With Hardware Accelerators: An Edge AI Application [J] . Mazzia Vittorio, Khaliq Aleem, Salvetti Francesco, Quality Control, Transactions . 2020,第期

机译：使用具有硬件加速器的嵌入式系统的实时Apple检测系统：Edge AI应用程序
3. Implementation and Experimentation of an Embedded Data Acquisition/Preprocessing System Based on a Hybrid Reconfigurable Hardware Accelerator for Inertial Measurements [J] . IEEE Transactions on Industry Applications . 2020,第2期

机译：基于混合可重构硬件加速器的惯性测量嵌入式数据采集/预处理系统的实现与实验
4. Interrupt Costs in Embedded System with Short Latency Hardware Accelerators [C] . Sebastien Lafond, Johan Lilius International Conference and Workshops on th e Engineering of Computer-Based Systems . 2008

机译：具有短延迟硬件加速器的嵌入式系统中的中断成本
5. Nanoprocessors: Configurable hardware accelerators for embedded systems. [D] . Zong, Lei. 2004

机译：纳米处理器：用于嵌入式系统的可配置硬件加速器。
6. Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators Using Time Compression Supporting Multiple Spike Codes [O] . Changqing Xu, Wenrui Zhang, Yu Liu, 2020

机译：使用时间压缩支撑多穗码的硬件尖峰神经加速器的吞吐量和效率
7. On improving real-time interrupt latencies of hybrid operating systems with two-level hardware interrupts [O] . Liu M, Liu D, Wang Y, 2011

机译：关于使用两级硬件中断来改善混合操作系统的实时中断延迟的问题

Interrupt Costs in Embedded System with Short Latency Hardware Accelerators

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