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Conception and Design of a RISC CPU for the Use as Embedded Controller within a Parallel Multimedia Architecture

机译：在并行多媒体体系结构中用作嵌入式控制器的RIsC CpU的概念和设计

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S. Dogimont; M. Gumm; F. Mombers; D. Mlynek; A. Torielli;
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年度 2007
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1. A Multimedia Architecture Extension for an Embedded RISC processor [J] . Ichiro Kuroda, Kouhei Nadehara IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 2001,第9期

机译：嵌入式RISC处理器的多媒体体系结构扩展
2. Architectural design of an RISC processor for programmable logic controllers [J] . Kyeonghoon Koo, Gab Seon Rho, Wook Hyun Kwon, Journal of systems architecture . 1998,第5期

机译：用于可编程逻辑控制器的RISC处理器的体系结构设计
3. Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs [J] . Daniel Ziener, Juergen Teich International journal of autonomous and adaptive communications systems . 2009,第3期

机译：嵌入式RISC CPU的运行时和容错控制流检查的概念
4. Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture [C] . Dogimont, S., Gumm, . 1997

机译：RISC CPU的概念和设计，用作并行多媒体体系结构中的嵌入式控制器
5. Architectural-physical co-design of 3D CPUs with micro-fluidic cooling. [D] . Serafy, Caleb. 2016

机译：具有微流体冷却功能的3D CPU的架构物理协同设计。
6. Design of a Mobile Brain Computer Interface-Based Smart Multimedia Controller [O] . Kevin C. Tseng, Bor-Shing Lin, Alice May-Kuen Wong, 2015

机译：基于移动脑计算机接口的智能多媒体控制器的设计
7. Architectural Design of a RISC Processor for Programmable Logic Controllers [O] . Kyeonghoon Koo, Gab Seon Rho, Wook Hyun Kwon, 1996

机译：可编程逻辑控制器RIsC处理器的结构设计
8. CODA: Coarse Grain Dataflow Architecture: Integration of a Parallel Architecture and RISC- [R] . Toda, K., Nishida, K., Uchibori, Y., 1990

机译：CODa：粗粒度数据流架构：并行架构和RIsC-的集成

Conception and Design of a RISC CPU for the Use as Embedded Controller within a Parallel Multimedia Architecture

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