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An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures

机译：动态可重构多FpGa架构的集成分区与综合系统

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Iyad Ouaiss; Sriram Govindarajan; Vinoo Srinivasan; Meenakshi Kaul; Ranga Vemuri;
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年度 1998
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2. Temporal partitioning of data flow graph for dynamically reconfigurable architecture [J] . Ouni B., Ayadi R., Mtibaa A. Journal of systems architecture . 2011,第8期

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3. Dynamically reconfigurable hardware-software architecture for partitioning networking functions on the SoC platform [J] . Youngmann Kim, E.K. Park, Sungwoo Tak Journal of systems and software . 2009,第10期

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4. Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints [C] . Preetham Lakshmikanthan, Sriram Govindarajan, Vinoo Srinivasan, IEEE International Parallel and Distributed Processing Symposium . 2000

机译：在互连，区域和延迟约束下的多FPGA架构合成的行为分区
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6. The dynamics of phase partition. A study of parameters affecting rat liver organelle partitioning in aqueous two-polymer phase systems. [O] . D Heywood-Waddington, T J Peters, I A Sutherland 1986

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7. Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures [O] . Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri, 1999

机译：可重构多FPGA架构的互连综合
8. Architectural Analysis of Dynamically Reconfigurable Systems [R] . 2010

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An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures

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