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Single transistor primitive for timing and power modelling of CMOS gates

机译：单晶体管原语用于CmOs门的定时和功率建模

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A. Chatzigeorgiou; S. Nikolaidis;
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年度 2000
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1. Analytical Model of Double Gate Stacked Oxide Junctionless Transistor Considering Source/Drain Depletion Effects for CMOS Low Power Applications [J] . Manikandan S., Balamurugan N. B., Nirmal D. Silicon . 2020,第9期

机译：考虑CMOS低功耗应用的源/漏耗竭效应的双栅堆叠氧化物连接晶体管的分析模型
2. Single-transistor latch-up and large-signal reliability in SOI CMOS RF power transistors [J] . F. Carrara, rnC.D. Presti, rnA. Scuderi, Solid-State Electronics . 2010,第9期

机译：SOI CMOS RF功率晶体管中的单晶体管闩锁和大信号可靠性
3. Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications [J] . Chung-Yu Wu, Ming-Chuen Shiau IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1990,第9期

机译：CMOS AND-OR-反相器和OR-AND-反相器门的高效物理时序模型及其应用
4. Single transistor primitive for modeling CMOS gates [C] . Chatzigeorgiou A., Nikolaidis S., Tsoukalas I. Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on . 1999

机译：用于模拟CMOS门的单晶体管原语
5. Synthesis of classical and non-classical CMOS transistor fault models mapped to gate-level for reconfigurable hardware-based fault injection [D] . Abedi, Raha. 2005

机译：映射到门级的经典和非经典CMOS晶体管故障模型的综合，用于基于硬件的可重构故障注入
6. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model [O] . Omnia S. Fadl, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, 2016

机译：具有实际门延迟模型的CMOS组合逻辑电路的准确动态功率估算
7. SINGLE TRANSISTOR PRIMITIVE FOR MODELING CMOS GATES [O] . A. Chatzigeorgiou, S. Nikolaidis, I. Tsoukalas 2008

机译：用于建模CmOs栅极的单晶体原始性

Single transistor primitive for timing and power modelling of CMOS gates

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