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Modeling and Evaluating the Scalability of Instruction Fetching in Superscalar Processors

机译：超标量处理器中指令获取的可扩展性建模与评估

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Mojtaba Shakeri; Abolfazl Toroghi Haghighat; Mohammad K. Akbari;
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年度 2008
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1. Modeled and measured instruction fetching performance for superscalar microprocessors [J] . Wallace S., Bagherzadeh N. IEEE Transactions on Parallel and Distributed Systems . 1998,第6期

机译：超标量微处理器的建模和测量指令获取性能
2. Analytical Models and Performance Analysis of Instruction Fetch on Superscalar processors [J] . Sun-Mo Kim, Jung-Woo Lee, Soo-Haeng Lee IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 2001,第6期

机译：超标量处理器上指令获取的分析模型和性能分析
3. An Instruction Throughput Model of Superscalar Processors [J] . Taha T.M., Scott Wills D. IEEE Transactions on Computers . 2008,第3期

机译：超标量处理器的指令吞吐量模型
4. Modeling and Evaluating the Scalability of Instruction Fetching in Superscalar Processors [C] . Mojtaba Shakeri, Abolfazl Toroghi Haghighat, Mohammad K. Akbari International Conference on Information Technology . 2007

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5. Issuing prioritization of instructions in the ready queue for superscalar processor. [D] . Gupta, Divya. 2016

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6. A Process Evaluation Protocol for Examining the Impact of Instructions for Correct Use of Child Car Seats Designed through a Consumer-Driven Process and Evaluated in a Field-Based Randomised Controlled Trial [O] . Julie Brown, Jane Elkington, Kate Hunter, 2020

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7. Modeled and measured instruction fetching performance for superscalar microprocessors [O] . Steven Wallace, Nader Bagherzadeh, Senior Member 1998

机译：超标量微处理器的建模和测量指令获取性能

Modeling and Evaluating the Scalability of Instruction Fetching in Superscalar Processors

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