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Timing Verification with Crosstalk for Transparently Latched Circuits

机译：采用串扰的时序验证，用于透明锁存电路

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Hai Zhou;
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年度 2003
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专利

1. Statistical timing verification for transparently latched circuits [J] . Ruiming Chen, Hai Zhou IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2006,第9期

机译：透明锁存电路的统计时序验证
2. Binning Optimization for Transparently-Latched Circuits [J] . Gong M., Zhou H., Li L., Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2011,第2期

机译：透明锁存电路的分级优化
3. Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations [J] . Li B., Chen N., Schlichtmann U. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2012,第11期

机译：具有减少的迭代和图变换的闩锁控制电路的统计时序分析
4. Timing Verification with Crosstalk for Transparently Latched Circuits [C] . Hai Zhou, PHai Zhou Workshop on New security paradigms workshop . 2009

机译：透明锁存电路的串扰时序验证
5. Crosstalk fault test generation and hierarchical timing verification in VLSI digital circuits. [D] . Lee, Kyung Tek. 1999

机译：VLSI数字电路中的串扰故障测试生成和分层时序验证。
6. Replication timing networks reveal a link between transcription regulatory circuits and replication timing control [O] . Juan Carlos Rivera-Mulia, Sebo Kim, Haitham Gabr, 2019

机译：复制定时网络揭示了转录调控电路与复制定时控制之间的联系
7. Binning Optimization based on SSTA for Transparently-Latched Circuits [O] . Min Gong, Hai Zhou, Jun Tao, 2015

机译：基于ssTa的透明锁存电路分档优化

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