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Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods

机译：使用轨迹分段方法自动提取数字门和锁存器的精确延迟/定时宏模型

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Sandeep Dabas; Ning Dong; Jaijeet Roychowdhury;
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年度 2008
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1. Timing macromodels for CMOS static set/reset latches and their applications [J] . Wu C.-Y., Li C. IEE Proceedings. Part E . 1988,第3期

机译：CMOS静态置位/复位锁存器的时序宏模型及其应用
2. ACCURATE GATE DELAY EXTRACTION FOR TIMING ANALYSIS OF BODY-BIASED CIRCUITS [J] . DONKYU BAEK, INSUP SHIN, YOUNGSOO SHIN Journal of circuits, systems and computers . 2013,第8期

机译：精确的门延迟提取，用于时序分析电路
3. General experimental method of parameter extraction for CMOS timing macromodels [J] . Wu C.-Y., Jang W.-Y. IEE Proceedings. Part I, Solid-State and Electron Devices . 1988,第2期

机译：CMOS时序宏模型参数提取的一般实验方法
4. Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods [C] . S. Dabas, Ning Dong, J. Roychowdhury, Conference on Asia South Pacific design automation . 2007

机译：使用轨迹分段方法自动提取数字门和锁存器的精确延迟/定时宏模型
5. Scalable trajectory methods for on-demand analog macromodel extraction. [D] . Tiwary, Saurabh Kumar. 2006

机译：用于按需模拟宏模型提取的可扩展轨迹方法。
6. An Accurate Timing Alignment Method with Time-to-Digital Converter Linearity Calibration for High-Resolution TOF PET [O] . Hongdi Li, Chao Wang, Shaohui An, -1

机译：具有高分辨率TOF PET的具有时间数字转换器线性校准的精确定时对准方法
7. 1Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods [O] . Sandeep Dabas, Ning Dong, Jaijeet Roychowdhury 2015

机译：使用轨迹分段方法对数字门和锁存器的精确延迟/定时宏模型进行1次提取
8. Delay Macromodels for the Timing Analysis of GaAs DCFL [R] . Kayssi, A. I., Sakallah, K. A. 1992

机译：延迟宏模型用于Gaas DCFL的时序分析

Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods

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