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Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation

机译：结合IEEE兼容和截断浮点乘法器以降低功耗

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Kent E. Wires; Michael J. Schulte; James E. Stine;
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年度 2001
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1. Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier with Reduced Power Dissipation [J] . Mohammad Moradinezhad Maryan, Seyed Javad Azhari, Mehdi Ayat, Journal of circuits, systems and computers . 2020,第3期

机译：紧凑的高速低误差四象限电流倍增器，功耗降低
2. 0.65 v class-AB current-mode four-quadrant multiplier with reduced power dissipation [J] . Kasimis C., Psychalinos C. AEU: Archiv fur Elektronik und Ubertragungstechnik: Electronic and Communication . 2011,第7期

机译：具有降低功耗的0.65 v AB类电流模式四象限乘法器
3. Design of Low Power Floating Point Multiplier with Reduced Switching Activity in Deep Submicron Technology [J] . S. Sivanantham International Journal of Applied Engineering Research . 2013,第7期

机译：深亚微米技术中降低开关活动的低功耗浮点乘法器设计
4. Combined IEEE compliant and truncated floating point multipliers for reduced power dissipation [C] . Wires, K.E., Schulte, . 2001

机译：结合IEEE兼容和截断浮点乘法器，以降低功耗
5. Architectural Improvements in IEEE-Compliant Floating-Point Multiplication [D] . Nguyen, Tuan Danh. 2018

机译：符合IEEE标准的浮点乘法的架构改进
6. Model of a Device-Level Combined Wireless Network Based on NB-IoT and IEEE 802.15.4 Standards for Low-Power Applications in a Diverse IoT Framework [O] . Juan Pablo García-Martín, Antonio Torralba 2021

机译：基于NB-IOT和IEEE 802.15.4在不同IOT框架中的低功耗应用标准的设备级组合无线网络模型
7. Reduced Power Dissipation Through Truncated Multiplication [O] . Michael J. Schulte, James E. Stine, John G. Jansen 1999

机译：通过截断乘法降低功耗

Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation

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