首页> 外文OA文献 >7.1 Approaches to Run-time and Standby Mode Leakage Reduction in Global Buses

【2h】

7.1 Approaches to Run-time and Standby Mode Leakage Reduction in Global Buses

机译：7.1全球公交车运行时和待机模式泄漏减少的方法

页面导航

著录项
引文网络
相似文献
相关主题

著录项

作者
Rahul Rao; Kanak Agarwal; Dennis Sylvester; Richard Brown; Kevin Nowka; Sani Nassif;
展开▼
作者单位

展开▼
年度 2013
总页数
原文格式 PDF
正文语种
中图分类

相似文献

外文文献
中文文献
专利

1. Performance Analysis of Leakage Current Reduction in Standby Mode of Zigbee SoC Using Active Mode Logic [J] . K. Parthiban, S. Sasikumar Journal of computational and theoretical nanoscience . 2018,第2期

机译：激活模式逻辑ZigBee SoC待机模式泄漏电流降低性能分析
2. Characterization and modeling of run-time techniques for leakage power reduction [J] . Yuh-Fang Tsai, Duarte D.E., Vijaykrishnan N., IEEE transactions on very large scale integration (VLSI) systems . 2004,第11期

机译：减少泄漏功率的运行时技术的表征和建模
3. Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation [J] . Wang Yu, Luo Hong, He Ku, Dependable and Secure Computing, IEEE Transactions on . 2011,第5期

机译：温度感知的NBTI建模以及减少待机漏电流技术对电路性能下降的影响
4. Approaches to run-time and standby mode leakage reduction in global buses [C] . Rahul Rao, Kanak Agarwal, Dennis Sylvester, Low Power Electronics and Design, 2004. ISLPED '04 . 2004

机译：全局总线中减少运行时和待机模式泄漏的方法
5. Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits. [D] . Chun, Jae Woong. 2012

机译：纳米级CMOS电路中降低待机泄漏功率的方法。
6. Compile- and run-time approaches for the selection of efficient data structures for dynamic graph analysis [O] . Benjamin Schiller, Clemens Deusser, Jeronimo Castrillon, -1

机译：选择编译时和运行时方法进行动态图分析的有效数据结构
7. Leakage Current Reduction by New Technique in Standby Mode [O] . A. Amirabadi, J. Jafari, A. Afzali-kusha, 2015

机译：待机模式下新技术减少漏电流

7.1 Approaches to Run-time and Standby Mode Leakage Reduction in Global Buses

著录项

引文网络

相似文献

相关主题

期刊订阅