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Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT

机译：基于petri网展开和增量saT的异步电路逻辑综合

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Victor Khomenko; Maciej Koutny; Alex Yakovlev;
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年度 2004
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1. Logic Synthesis for Asynchronous Circuits Based on STG Unfoldings and Incremental SAT [J] . Victor Khomenko, Maciej Koutny, Alex Yakovlev Fundamenta Informaticae . 2006,第1a2期

机译：基于STG展开和增量SAT的异步电路逻辑综合
2. Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits [J] . Cunxi Yu, Xiangyu Zhang, Duo Liu, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2017,第10期

机译：基于增量SAT的伪装逻辑电路逆向工程
3. GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis [J] . Aoxiang Tang, Niraj K. Jha IEEE transactions on very large scale integration (VLSI) systems . 2016,第3期

机译：GenFin：使用增量统计分析的基于遗传算法的多目标统计逻辑电路优化
4. Logic synthesis for asynchronous circuits based on Petri net unfoldings and incremental SAT [C] . Khomenko, V., Koutny, . 2004

机译：基于Petri网展开和增量SAT的异步电路逻辑综合
5. Formal Verification Methodology for Asynchronous Sleep Convention Logic Circuits Based on Equivalence Verification [D] . Hossain, Mousam 2019

机译：基于等效验证的异步睡眠会议逻辑电路的正式验证方法
6. Logic Synthesis of Recombinase-Based Genetic Circuits [O] . Tai-Yin Chiu, Jie-Hong R. Jiang -1

机译：基于重组酶的遗传电路的逻辑综合
7. Modelling, Analysis and Synthesis of Asynchronous Control Circuits Using Petri Nets [O] . A. V. Yakovlev, A. M. Koelmans, A. Semenov, 1996

机译：基于petri网的异步控制电路建模，分析与综合
8. Computing Shortest Violation Traces in Model Checking Based on Petri Net Unfoldings and SAT [R] . Khomenko, V. 2004

机译：基于petri网展开和saT的模型检测中最短违规痕迹的计算

Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT

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