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A CPPLL Hierarchical Optimization Methodology Considering Jitter, Power and Locking Time

机译：考虑抖动，功率和锁定时间的CppLL分层优化方法

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Jun Zou; Daniel Mueller; Helmut Graeb; Ulf Schlichtmann;
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年度 2008
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1. Practical analysis of clock jitter reduction techniques under power supply noise for continuous-time delta-sigma modulators [J] . Tang Hua Analog Integrated Circuits and Signal Processing . 2016,第2期

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2. Low-Power Methodology Kit Accelerates Wireless and Consumer Chip Designs: Optimized flows. IP and modular methodology reduce risk and development time [J] . John Donovan Portable Design: The Engineer's Resource for Portable Applications . 2007,第5期

机译：低功耗方法论套件可加速无线和消费芯片设计：优化流程。 IP和模块化方法降低了风险并缩短了开发时间
3. A continuous-time delta-sigma modulator for 802.11a/b/g WLAN implemented with a hierarchical bottom-up optimization methodology [J] . Tom Eeckelaert, Raf Schoofs, Michiel Steyaert, Analog Integrated Circuits and Signal Processing . 2008,第1期

机译：采用分层的自底向上优化方法实现的802.11a / b / g WLAN连续时间delta-sigma调制器
4. A CPPLL hierarchical optimization methodology considering jitter, power and locking time [C] . Jun Zou, Daniel Mueller, Helmut Graeb, Annual conference on Design automation;Conference on Design automation . 2006

机译：考虑抖动，功耗和锁定时间的CPPLL分层优化方法
5. Analysis, measurement and optimization of jitter in phase -locked loops [D] . Vamvakos, Socrates D. 2005

机译：锁相环中抖动的分析，测量和优化
6. Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications [O] . Bilal I. Abdulrazzaq, Omar J. Ibrahim, Shoji Kawahito, 2016

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7. An asymmetric dual-loop feedback scheme with optimized second delay time to suppress spurious tones and timing jitter of self-mode-locked quantum dash lasers [O] . Asghar, Haroon, McInerney, John. G. 2017

机译：具有优化的第二延迟时间的非对称双环反馈方案抑制自锁模量子冲击的杂散音和定时抖动激光器

A CPPLL Hierarchical Optimization Methodology Considering Jitter, Power and Locking Time

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