首页> 外文OA文献 >A Novel On-chip Delay Measurement Hardware for Efficient Speed-Binning

【2h】

A Novel On-chip Delay Measurement Hardware for Efficient Speed-Binning

机译：一种用于高效速度分档的新型片上延迟测量硬件

页面导航

著录项
引文网络
相似文献
相关主题

著录项

作者
A. Raychowdhury; S. Ghosh; K. Roy;
展开▼
作者单位

展开▼
年度 2005
总页数
原文格式 PDF
正文语种
中图分类

相似文献

外文文献
中文文献
专利

1. Hardware-Efficient VLSI Design for Cascade Support Vector Machine with On-Chip Training and Classification Capability [J] . Loukrakpam Merin, Choudhury Madhuchhanda Circuits, systems and signal processing . 2020,第10期

机译：用于片上培训和分类能力的级联支持向量机的硬件高效VLSI设计
2. Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning [J] . Chien-Min Ou, Hui-Ya Li, Wen-Jyi Hwang Sensors . 2012,第9期

机译：片上学习的高效k赢家通吃的所有竞争性学习硬件架构
3. Frequent loop detection using efficient nonintrusive on-chip hardware [J] . Gordon-Ross A., Vahid F. IEEE Transactions on Computers . 2005,第10期

机译：使用高效的非侵入式片上硬件进行频繁的环路检测
4. A novel on-chip delay measurement hardware for efficient speed-binning [C] . Raychowdhury, A., Ghosh, . 2005

机译：一种新颖的片上延迟测量硬件，可实现高效的速度合并
5. Detecting delay anomalies introduced by hardware trojans using chip averaging and an on-chip high resolution embedded test structure. [D] . Ismari, Dylan. 2016

机译：使用芯片平均和片上高分辨率嵌入式测试结构来检测硬件木马引入的延迟异常。
6. Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning [O] . Chien-Min Ou, Hui-Ya Li, Wen-Jyi Hwang 2012

机译：片上学习的高效k-胜者为王-所有竞争性学习硬件架构
7. On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications [O] . Octavian Petre, Hans G. Kerkhoff 2015

机译：用于高速芯片间数据通信的数字延迟线的片上抽头延迟测量

A Novel On-chip Delay Measurement Hardware for Efficient Speed-Binning

著录项

引文网络

相似文献

相关主题

期刊订阅